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    Home - AI - Negative Capacitance Breaks GaN Transistor Limits
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    Negative Capacitance Breaks GaN Transistor Limits

    TechurzBy TechurzJuly 29, 2025Updated:May 10, 2026No Comments5 Mins Read
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    Negative Capacitance Breaks GaN Transistor Limits
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    Integrating an electronic material that exhibits a strange property called negative capacitance can help high-power gallium nitride transistors break through a performance barrier, say scientists in California. Research published in Science suggests that negative capacitance helps sidestep a physical limit that typically enforces trade-offs between how well a transistor performs in the “on” state versus how well it does in the “off” state. The researchers behind the project say this shows that negative capacitance, which has been extensively studied in silicon, may have broader applications than previously appreciated.

    Electronics based on GaN power 5G base stations and compact power adapters for cellphones. When trying to push the technology to higher frequency and higher power operations, engineers face trade-offs. In GaN devices used to amplify radio signals, called high-electron-mobility transistors (HEMTs), adding an insulating layer called a dielectric prevents them from wasting energy when they’re turned off, but it also suppresses the current flowing through them when they are on, compromising their performance.

    To maximize energy efficiency and switching speed, HEMTs use a metal component called a Schottky gate, which is set directly on top of a structure made up of layers of GaN and aluminum gallium nitride. When a voltage is applied by the Schottky gate, a 2D electron cloud forms inside the transistor. These electrons are zippy and help the transistor switch rapidly, but they also tend to travel up toward the gate and leak out. To prevent them from escaping, the device can be capped with a dielectric. But this additional layer increases the distance between the gate and the electron cloud. And that distance decreases the ability of the gate to control the transistor, hampering performance. This inverse relationship between the degree of gate control and the thickness of the device is called the Schottky limit.

    “Getting more current from the device by adding an insulator is extremely valuable. This cannot be achieved in other cases without negative capacitance.” —Umesh Mishra, University of California, Santa Barbara

    In place of a conventional dielectric, Sayeef Salahuddin, Asir Intisar Khan, and Urmita Sikderan, electrical engineers at University of California, Berkeley, collaborated with researchers at Stanford University to test a special coating on GaN devices with Schottky gates. This coating is made up of a hafnium oxide layer frosted with a thin topping of zirconia oxide. The 1.8-nanometer-thick bilayer material is called HZO for short, and it’s engineered to display negative capacitance.

    HZO is a ferroelectric. That is, it has a crystal structure that allows it to maintain an internal electrical field even when no external voltage is applied. (Conventional dielectrics don’t have this inherent electrical field.) When a voltage is applied to the transistor, HZO’s inherent electric field opposes it. In a transistor, this leads to a counterintuitive effect: A decrease in voltage causes an increase in the charge stored in HZO. This negative capacitance response effectively amplifies the gate control, helping the transistor’s 2D electron cloud accumulate charge and boosting the on-state current. At the same time, the thickness of the HZO dielectric suppresses leakage current when the device is off, saving energy.

    “When you put another material, the thickness should go up, and the gate control should go down,” Salahuddin says. However, the HZO dielectric seems to break the Schottky limit. “This is not conventionally achievable,” he says.

    “Getting more current from the device by adding an insulator is extremely valuable,” says Umesh Mishra, a specialist in GaN high-electron-mobility transistors at the University of California, Santa Barbara, who was not involved with the research. “This cannot be achieved in other cases without negative capacitance.”

    Leakage current is a well-known problem in these kinds of transistors, “so integrating an innovative ferroelectric layer into the gate stack to address this has clear promise,” says Aaron Franklin, an electrical engineer at Duke University, in Durham, N.C. “It certainly is an exciting and creative advancement.”

    Going Further With Negative Capacitance

    Salahuddin says the team is currently seeking industry collaborations to test the negative capacitance effect in more advanced GaN radio-frequency transistors. “What we see scientifically breaks a barrier,” he says. Now that they can break down the Schottky limit in GaN transistors under lab conditions, he says, they need to test whether it works in the real world.

    Mishra agrees, noting that the devices described in the paper are relatively large. “It will be great to see this in a device that’s highly scaled,” says Mishra. “That’s where this will really shine.” He says the work is “a great first step.”

    Salahuddin has been studying negative capacitance in silicon transistors since 2007. And for much of that time, says Mishra, Salahuddin has been subject to intense questioning after every conference presentation. Nearly 20 years later, Salahuddin’s team has made a strong case for the physics of negative capacitance, and the GaN work shows it may help push power electronics and telecom equipment to higher powers in the future, says Mishra. The Berkeley team also hopes to test the effect in transistors made from other kinds of semiconductors including diamond, silicon carbide, and other materials.

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